1. Technical field
The present disclosure relates to integrated circuits comprising transistors distributed in several levels. Such integrated circuits comprise a stack of at least two semiconductor layers separated by an insulating layer. This is often referred to as three-dimensional (3D) integration, and 3D integrated circuits.
2. Discussion of the Related Art
Increasing the component density in integrated circuits generally is a constant concern. A solution is to manufacture integrated circuits comprising components distributed in several levels of semiconductor layers.
FIG. 1 is a cross-section view schematically showing an example of a 3D integrated circuit comprising transistors distributed in two levels, the integrated circuit being formed on an SOI-type (“Silicon-On-Insulator”) wafer 1.
Wafer 1 comprises a semiconductor substrate 3 covered with an insulating layer 5, currently called BOX (“Buried OXide”), itself coated with a semiconductor layer 7. A conductive layer 4, called rear electrode, may be present in wafer 1 under insulating layer 5.
A MOS transistor T1 formed in semiconductor layer 7 is illustrated. Transistor T1 comprises a conductive gate 9 insulated from the upper surface of semiconductor layer 7 by a gate insulator 11. Spacers 13 surround gate 9. Source and drain areas 15 extend in layer 7 on either side of gate 9. In the following description, transistor T1 is called the lower transistor.
An insulating layer 29 separates semiconductor layer 7 comprising transistor T1 from another semiconductor layer, 17, comprising other MOS transistors such as transistor T2. Transistor T2 comprises a gate 19 arranged on a gate insulator 21, spacers 23, and source and drain regions 25. An insulating layer 33 covers semiconductor layer 17 and transistor T2. In the following description, transistor T2 is called the upper transistor.
Contacts 35 crossing insulating layer 33 provide access to source and drain regions 25 and to gate 19 of transistor T2. Contacts crossing insulating layer 33 and insulating layer 29, not shown, provide access to source and drain regions 15 and to gate 9 of transistor T1.
An example of a method enabling to obtain an integrated circuit such as that illustrated in FIG. 1 is the following.
MOS transistors such as transistor T1 are formed on a wafer 1 by implementing manufacturing steps currently used for MOS transistor manufacturing. Once transistors T1 have been formed, an insulating layer 30 is deposited above the upper surface of semiconductor layer 7 of wafer 1 and above transistors T1, after which insulating layer 30 is leveled.
One of the surfaces of another semiconductor wafer, covered with an insulator layer 31, is then applied on insulating layer 30, to obtain a bonding between wafer 1 comprising transistors T1 and covered with layer 30 and the other wafer. After the bonding, the other wafer is thinned to obtain the desired thickness for semiconductor layer 17.
At this stage of the process, above semiconductor layer 7 comprising transistors T1, a stack of an insulating layer 29, formed of insulating layers 30 and 31, and of a semiconductor layer 17 has been obtained. Manufacturing steps currently used for the manufacturing of MOS transistors are then implemented to manufacture MOS transistors such as transistor T2 in semiconductor layer 17.
In certain applications, it is desirable to be able to dynamically and independently adjust the threshold voltage of the lower transistor and the threshold voltage of the upper transistor.
The threshold voltage of lower transistor T1 may be adjusted by applying a variable voltage to rear electrode 4.
Rear electrode 4 is generally formed by high-energy implantation of dopant elements in wafer 1 before the forming of transistor T1. After this implantation step, an anneal for activating the dopant elements is performed, generally at a relatively high temperature, for example, at a temperature greater than 900° C.
Since semiconductor layer 17 supporting upper transistor T2 is separated from semiconductor layer 7 supporting lower transistor T1 by an insulating layer 29, it is not possible to implant dopant elements in insulating layer 29 to also form a rear electrode under upper transistor T2 in order to adjust its threshold voltage.